The present invention relates generally to data storage arrays of integrated circuits or semiconductor chips, such as dynamic random access memory (DRAM) devices. More particularly, the present invention is directed towards the utilization of memory devices having faulty memory locations.
A memory unit is an integral part of any microcomputer system and its primary purpose is to store programs and data. Dynamic random access memory ("DRAM") is one example of a memory unit. DRAM devices are usually assembled on a single in-line memory module ("SIMM"). Typically, on a SIMM printed circuit board, there are several DRAMs arranged in a manner allowing simultaneous access to the stored data. These DRAMs, however, are sometimes manufactured with faulty memory locations. It is desired to incorporate DRAMs having faulty memory locations on a SIMM while still maintaining proper SIMM functionality.
One technique of utilizing DRAMs having faulty locations is to incorporate an application specific integrated circuit ("ASIC") on the SIMM. The ASIC is programmed to redirect data addressed to the faulty locations to another source of back-up memory on the SIMM, so that faulty locations are avoided. In another technique, DRAMs are tested individually before and after assembly onto a SIMM printed circuit board. More often, because of interferences due to mounting on the SIMM, the data gathered while testing the DRAMs before SIMM assembly is used to assist in programming the ASIC to mask the faulty locations. As a result of testing the DRAMs, the extent and layout of the faulty locations are determined by generating a "fail map" for each DRAM. The ASIC is programmed to mask out faulty locations by referring to and matching the faulty locations in the generated fail map. As will be apparent in the following paragraph, this form of masking process using a fail map is often inefficient, inaccurate and time consuming.
Furthermore, several memory systems utilizing fail maps exist in the prior art. A programmable read only memory ("PROM") utilized to recognize the addresses of faulty memory locations to cause a redundant memory to be selected for data storage was described in Tsang (U.S. Pat. No. 4,376,300). A separate permanent memory used to record bad cells and devices for continuous reference to avoid access to defective cells was described in Anderson et al. (U.S. Pat. No. 4,493,075). A MAP identifying memory chips having faulty memory locations was used to connect data lines to a good location in a spare memory chip as disclosed in MacDonald (U.S. Pat. No. 5,406,565). Another memory system compares the address of a data signal to a stored address of a defective memory cell and, if they agree, redirects the data signal to a spare memory cell (Fujiwara, U.S. Pat. No. 5,475,648). These systems and methods are time consuming because the matching process must sort through relatively large fail maps to try and locate a matching map. Also, they are inaccurate because the faults generated when the DRAMS are on a SIMM will likely only show a portion of the failures that were detected in the DRAM fail maps generated prior to assembly on a SIMM. Moreover, should too many defective memory locations be present in the main memory devices, these prior art techniques may be susceptible to overcrowding the spare memory device(s), or overlapping a redirected data signal on a defective memory location in the spare memory. These problems lead to the need for more error correction algorithms, reduced memory capacity, and, consequently, reduced data transfer rates.
In view of the foregoing problems, there is a need to manage memory devices having faulty memory locations efficiently and accurately, while maintaining simple and cost-effective designs.